czwartek, 13 grudnia 2012

PC/104 DIO Card - final form

I have worked on the schematic of the digital I/O card based on the 82C55 for the SBC computer I have recently acquired and came with a final schematic - simplified as much as possible - and a PCB project. Here it is:

The schematic is simplified, yet it does comply with the PC/104 or ISA standard. There are three buffers - two for generic use - addresses and control signals (AEN, IOR, IOW, and RESET). Third buffer is utilized for data bus, and its control is a bit more tricky - the direction of the buffer is controlled by the buffered IOR signal and it is enabled by the ADDR signal that is generated in the addres decoder. For that part I have utilized a 8 bit comparator, so I can place the device in any address in the whole address space on 10 bits. Two LSB bits of the address are only buffered and feed to the 82C55 as it does all the magic. In that way I got rid of the strange address decoder of the old project and simplified generation of the Chip Select signal for the 82C55 - now it is selected by the ADDR signal from the address decoder.

The board layout is now much simpler with enough space to fit and DC25 connector, like shown below.

I plan to send the project soon to have PCBs made and start soldering the whole thing. I have several ideas how to use this PC, but can not say anything for now. I'll keep you informed :).

Brak komentarzy:

Prześlij komentarz